Hardware Design Engineer

Systems Technology Division,
Hewlett-Packard Company,
3404 East Harmony Road,
Fort Collins, CO, 80525,
(from Jan 1998)




Main interest is digital VLSI - both component research and development, and CAD environment design.

Degrees: Mathematics, Computer Science and Electrical Engineering.

Employment: one year in ASIC design at Hitachi Central Research Laboratory, Tokyo; seven years as lecturer in VLSI Design and Project Management at the University of Edinburgh; three years in industrial VLSI and CAD development at ES2, Bracknell.

Commercial products: ROM generator and parameterizable logic module library.

Publications: VLSI articles on Memory design, CAD development and DSP components; and over a dozen articles on Management skills with a book published by the IEEE.

Digital CMOS VLSI design skills: layout, design rule checking, circuit level simulation (HSPICE), standard-cell design, schematic capture, layout vs schematic, place-and-route, behavioural simulation (Verilog), CAD development, digital design, design quality assurance, CADENCE design environment and tool development with Skill.

Programming skills: C, Lisp, Skill, Verilog


The University of Edinburgh, UK (1983-86)

The University of Cambridge, UK (1979-83)


SENIOR VISITING RESEARCHER, Hitachi Central Research Lab, Tokyo, Japan (Oct 94 - Sept 95)

Member of Multi-Media group. Focused on the design of a VLSI accelerator-module for MPEG audio encoding. Devised silicon implementation of discrete Fourier transform with new bit-serial architecture avoiding all control signals except an initial reset. The technique also led to the design of a hardware accelerator for the discrete cosine transform. The designs were specified in (C-generated!) Verilog and implemented through netlist conversion and layout using Cadence place-and-route tools[20, 25, 26, 29-34].

LECTURER, University of Edinburgh, Scotland, UK (1989- 1997)

VLSI Design: third-year undergraduate course (wrote text book[1] ) and design laboratory. Initiated a unique collaborations with Cadence UK resulting in the donation of software (worth over a million pounds) to establish the Cadence Laboratory for Scotland and an annual student prize of a trip to Cadence - in California.

Project Management: three week intensive Masters module and a first-year undergraduate course. Proposed and devised the courses from scratch. The focus was on the skills which a graduate engineer needs to manage small teams and small projects as determined by a survey[45] of employers of past graduates. The organization and philosophy were published in both professional and research literature[43, 44, 56-60], and the material as a series of ten articles in the IEE Engineering Management Journal[46-55] and a book[41] which has been reprinted[42] in the IEEE Engineers Guide to Business series.

Courses attended: To acquire skills and knowledge for the MEng course, attended several industrial courses:

Course Company Year
Team Work Hewlett-Packard 1990
Management I Royal Bank of Scotland 1990
Project Planning British Telecom 1991
Making Meetings Matter EU Personnel Office 1991
People Management Standard Life 1991

Awards: Premium Award for the IEE Engineering Management Journal 1992; Commendation in the ESSO UK prize for "transferable skills in engineering" in the Partnership Trust Awards (a national "scheme for commending innovation in teaching and learning in higher education") 1994; promotion to Senior Lecturer in 1995.

Consultancy: EuCAD (the European R&D division of Cadence), VLSI Vision Ltd (the producers of the Peach and Imputer "camera on a chip"), and Motorola, East Kilbride.

Working for Scottish Enterprise, through Cadence, member of think tank: "group of top academic experts from around the world", to define vision and curriculum for the System Level Integration Institute in Scotland as part of Project Alba, 1997.

Research activity in VLSI Design: see below.

PROJECT LEADER, European Silicon Structures (ES2), Bracknell, UK (1986-89)

Softmacro Development Group: originated definition of new product/documentation format. Given sole responsibility for recruiting and managing new group; reviewed and updated base library elements; performed complete revision of existing softmacros; specified and implemented new parameterizable library with strategic library cells to assist in the penetration of new markets; devised and implemented automatic Quality Assurance procedure for cell-macro design.

Parameterized ROM Generator: sole responsibility from initial design through to prototype testing and documentation. Developed with Cadence software, the project consisted of schematic entry and design analysis using SPICE, leaf-cell layout for 2um CMOS, critical path analysis; software in SKILL for HCI; automatic layout; creation of schematic, symbol, abstract views, and Silos model; and automatic post-commissioned verification using DRC and simulation of extracted layout. The design was then ported across design rules to 1.5um CMOS, and finally integrated in ES2's solo1400 software with an IMP functional model.

General Activities: research into embedded-controller design in terms of the CAD interface and environment[10, 11]. Devised and promoted method by which customers could include full-custom modules within ES2's semi-custom layout environment. Provided support to sales and marketing through informal presentations to customers. Liaised with ES2's partners in DTI Behavioural Compilers Project. Coordinated final phases of Alvey DSP collaboration with Edinburgh University including complete revision of workplan to obtain final contract. Initiated successful LINK application with Southampton University and Lucas Research.


Overview My interests are primarily in digital VLSI design. They include the direct implementation of DSP algorithms on silicon, clocking strategies for large designs, circuit design, low-power techniques, and effective design methodologies.

Bit-serial correlator with self-generating clock The issue of clock distribution in large MOS designs led to the idea of constructing a system of independent modules with primarily bit-serial architectures driven by locally generated clocks and interfaced by hand-shaking protocols. In this view, the internal clock for each module is generated using its own distribution network as a ring oscillator. Thus, fast local clocks achieve rapid bit-serial computations in a relatively small area. To explore these ideas, the design of a spread-spectrum correlator was considered[12]. The device has an input data work of 4-bits which is correlated with 512 binary taps at a (typical) sample rate of 2.4 MHz producing a full precision 13-bit sum. The design consists of 3.5K bit-registers in 70 mm-sq using a 1.2µ process. The clock feedback loop includes several buffer stages running in the opposite direction to the data-flow (to avoid race hazards).

CAD for skew-free clock distribution The main deficiency was that the clock feedback path was unnecessarily long with respect to the optimal buffering of the clock signals; work thus began on overcoming the well-known problems of clock skew. The aim was to automate the generation of a balanced (for signal delay) clock-distribution network. My approach was to exploit a feature of the Cadence design software which allows the modification of layout according to a simple parameter even after place and route. Thus a good initial guess for a balanced network can be updated to be fully balanced after the actual routing and interconnect capacitances are known[5, 9]. The effect of fixed interconnect capacitances on the buffer taper factor has been derived[17].

Low-power PLA circuit design The above work implicitly assumed a single-phase clock and the use of CMOS technology. One of the most common sub-modules in VLSI is the Programmable Logic Array (PLA); its implementation in single-phased CMOS is achieved using either pseudo-NMOS which introduces static power consumption, or dynamic techniques with discharge paths of transistors (to form a NAND gate) which introduces delay. Combining these two approaches, I proposed a hybrid design style which achieves the high speed of the first with far lower static-power consumption[6].

Augmented self-generating clocks One problem associated with the self-generating clock is that the delay between latches is limited to that of the ring oscillator and so designs must avoid long combinatorial logic delays. This restriction can be reduced by augmenting the oscillator path to include such delay chains (using self-timed logic or delay matching). A square-root algorithm which avoids multiplication was implemented to test this idea[7]. In general, the idea is to use local, creative clocking and a a novel circuit for the controlled-generation of a clock's falling edge has been proposed[40].

Twos-complement addition and redundant-number conversion During an investigation into logic for conversion from redundant-binary to twos-complement numbers, the direct use of conversion logic as a twos-complement adder was noticed in two special cases[15, 16]. A formal proof of the general equivalence has been derived[8].

Adder design This interest in adder logic has been continued in the design of a high-speed wide adder[37] and circuit enhancements to improve the performance of multiple output domino logic[39].

Latch design Recent activity on latch design has resulted in the discovery of problems with two published latch designs[18, 21, 22] and a proposal for a low-power double-edge triggered latch circuit[19].

Asynchronous logic New two-phase micropipeline controller logic has been designed which offers superior performance to all other techniques[13, 35]. It has been verified using formal techniques[28] and included in a novel parallel-serial conversion architecture[38].

Miscellaneous As part of background research, review articles have been written on low-power design[24], Discrete Cosine Transforms[36] and Verilog HDL[27]. Work has also been performed on Viterbi implementations[14] and a digital design for the Tower of Hanoi[23] has resulted from a student laboratory.

Citations The Doctoral work on content-addressable memory[3, 4] is cited in IEE Proceedings, IEEE Journal of Solid-State Circuits, and IEEE Micro, and is described in full within a chapter of Advances in Computers by Academic Press (1992).

A paper on skew-free clock distribution[5] was selected for IEEE reprints[9]

The low-power single-phase programmable-logic-array[6] has been incorporated in standard text books: Weste and Eshraghian - 2nd edition, 1993; and Bellaouar and Elmasry - 1995), and cited in IEEE Trans Neural Networks (and implemented in silicon).

The survey on low-power digital techniques[24] is cited in Microelectronics Journal; and the low-cost sorting architecture[20] is cited in Nuclear Instruments & Methods in Physics Research.


  1. G.M. Blair, MOS Circuit Design: an explanation , Chartwell-Bratt, 1992. ISBN-0-86238-307-2
  2. G.M. Blair, Content Addressable Memory: Design and usage for general purpose computing , PhD Thesis, The University of Edinburgh, 1986.
  3. G.M. Blair, "A Content Addressable Memory with a Fault-Tolerance Mechanism", IEEE JSSC , vol. SC-22, no. 4, pp. 614-616, Aug 1987.
  4. G.M. Blair and P.B. Denyer, "Content addressability: an exercise in the semantic matching of hardware and software design", IEE Proceedings Part E , vol. 136, no. 1, pp. 41-47, Jan 1989.
  5. G.M. Blair, "Skew-Free Clock Distribution for Standard-Cell VLSI Designs", Proc. IEE Pt. G , vol. 139, no. 2, pp. 265-268, April 1992.
  6. G.M. Blair, "PLA design for single-clock CMOS", IEEE JSSC , vol. 27, no. 8, pp. 1211-1213, Aug 1992.
  7. G.M. Blair, "Self-generating clocks using an augmented distribution network", Proc. IEE Circuits, Devices and Systems , vol. 144, no. 4, pp. 219-222, Aug 1997.
  8. G.M. Blair, "The equivalence of twos-complement addition and the conversion of redundant-binary to twos-complement numbers", IEEE Trans Circuits & Systems I , accepted for 1998.
  9. G.M. Blair, "Skew-Free Clock Distribution for Standard-Cell VLSI Designs", in Clock Distribution Networks in VLSI Circuits and Systems , ed. E. G. Friedman, pp. 211-213, IEEE Press, Piscataway, New Jersey, 1995. (reprint of paper) ISBN 0-7803-1058-6
  10. R.M. Marshall, G.M. Blair, and J.P. Gray, "ASIC-BASIC: An Application-Description Language and Compiler", Proc. 8th Int. Custom Microelectronics Conference , pp. 29/0-7, 1988.
  11. R.M. Marshall, G.M. Blair, and J.P. Gray, "Synthesis of Heterogeneous Systems: A Language and Compiler for Real-world Applications", EURO ASIC , 1989.
  12. G.M. Blair, "Bit-serial Correlator with Novel Clocking Scheme", Proc ESSCIRC , pp. 157-160, 1991.
  13. G.S. Taylor and G.M. Blair, "Reduced complexity two-phase micropipeline latch controller", ESSCIRC 97 , pp. 304-307, Sept 1997.
  14. J.M. Dobson, G.M. Blair, and B. Mulgrew, "Viterbi Equalization: low-power VLSI module design", Proc. IDSPCC 1996 , pp. 253-260, June 1996.
  15. J.M. Dobson and G.M. Blair, "Fast twos complement VLSI adder design", IEE Electronics Letters , vol. 31, no. 20, pp. 1721-1722, Sept 1995.
  16. G.M. Blair, "Low-area, pipelined conversion from signed-binary, to twos-complement, number representation.", IEE Electronics Letters , vol. 32, no. 20, pp. 1866-1867, 26th Sept 1996.
  17. G.M. Blair, "CMOS Buffer Tapering with Interconnect Capacitances", IEE Electronics Letters , vol. 32, no. 21, pp. 1984-1985, 10th Oct 1996.
  18. G.M. Blair, "Comment on new differential flipflop from Yuan and Svensson", IEE Electronics Letters , vol. 32, no. 23, pp. 2125-2126, Nov 1996.
  19. G.M. Blair, "Low-power double-edge triggered flip-flop", IEE Electronics Letters , vol. 33, no. 10, pp. 845-847, 12th May 1997.
  20. G.M. Blair, "Low cost sorting circuit for VLSI", IEEE Trans Circuit & Syst (express letter) , pp. 515-516, June 1996.
  21. G.M. Blair, "Comments on: A robust single phase clocking for low power, high-speed VLSI applications", IEEE JSSC (express letter) , vol. 31, no. 12, pp. 2060-2061, Dec 1996.
  22. G.M. Blair, "Comments on: New single-clock CMOS latches and flipflops with improved speed and power savings", IEEE JSSC (express letter) , vol. 32, no. 10, pp. 1610-1611, Oct 1997.
  23. G.M. Blair, "A Simple Digital Circuit for the Towers of Hanoi Problem", IEEE Trans Education (express letter) , vol. 40, no. 4, pp. 287-288, Nov 1997.
  24. G.M. Blair, "Designing Low-Power Digital CMOS", IEE Electronics & Communication Engineering Journal , vol. 6, no. 5, pp. 229-236, Oct 1994.
  25. G.M. Blair, "A review of the discrete Fourier transform. Part 1: manipulating the powers of two", IEE Electronics & Communication Engineering Journal , vol. 7, no. 4, pp. 169-177, Aug 1995.
  26. G.M. Blair, "A review of the discrete Fourier transform. Part 2: non-radix algorithms, real transforms and noise", IEE Electronics & Communication Engineering Journal , vol. 7, no. 5, pp. 187-194, Oct 1995.
  27. G.M. Blair, "Verilog - accelerating digital design", IEE Electronics & Communication Engineering Journal , vol. 9, no. 2, pp. 68-72, April 1997.
  28. G.S. Taylor, G. Clark, and G.M. Blair, "Application of CCS to verify a new two-phase micropipeline latch controller", Proceedings 2nd UK Asynchronous Forum , July 1997.
  29. G.M. Blair, "The discrete Fourier transform: algorithms and digital implementation for audio application", Hitachi Kenpo , no. 22708, 1995.
  30. G.M. Blair, "Bit-serial 8x8-pt DCT VLSI accelerator module", Hitachi Kenpo , no. 22931, 1995.
  31. G.M. Blair, "Program generation of IC standard-cell netlists for fully-parallel bit-serial discrete-Fourier-transform hardware", Hitachi Kenpo , no. 22932, 1995.
  32. G.M. Blair, "Hardware acceleration for the DFT", Hitachi Kenpo , no. 23020, 1995.
  33. G.M. Blair, "A Bit-serial complex multiplier", Japanese Patent #319500632 , 1995.
  34. G.M. Blair, "Bit-serial cascade networks with sign-extended data for fixed coefficient transforms", IEEE Trans VLSI Systems , submitted in 1997.
  35. G.S. Taylor and G.M. Blair, "Reduced complexity two-phase micropipeline latch controller", IEEE JSSC , submitted in 1997.
  36. G.S. Taylor and G.M. Blair, "Design of the Discrete Cosine Transform", IEE Proc - Comp and Dig Tech , submitted in 1997.
  37. G.M. Blair, "Multiple output domino logic for compact, wide adder design", IEE Proc - Comp and Dig Tech , submitted in 1997.
  38. G.S. Taylor and G.M. Blair, "Two-dimensional micropipelines: for parallel to serial data conversion", IEE Electronics Letters , accepted for 1998.
  39. G.M. Blair, "Circuit improvements for high-speed domino logic: for the manchester carry chain", IEE Electronics Letters , submitted in 1997.
  40. G. Morris and G.M. Blair, "Local generation of the falling clock edge for silicon resource sharing", IEE Electronics Letters , accepted for 1998.
  41. G.M. Blair, Starting to Manage: the essential skills , Chartwell-Bratt, 1993. ISBN-0-86238-336-6
  42. G.M. Blair, Starting to Manage: the essential skills , IEEE (Engineers Guides to Business), 1995. ISBN-0-7803-2295-9
  43. C.M. Robinson and G.M. Blair, "Writing skills training for engineering students in large classes", Higher Education , vol. 30, pp. 99-114, July 1995.
  44. G.M. Blair, "Project Management Skills for Electrical Engineers", Proc. 6th Conf. The Teaching of Electronic Engineering Degree Courses" , pp. 45/1-8, The University of Hull, April 1992.
  45. G.M. Blair, "The Need for Project Management Skills in Newly Graduated Electrical Engineers", Project , vol. 4, no. 3, pp. 24-5, June 1991.
  46. G.M. Blair, "Groups that work", IEE Engineering Management Journal , vol. 1, no. 5, pp. 219-223, Oct 1991.
  47. G.M. Blair, "Presentation Skills for Emergent Managers", IEE Engineering Management Journal , vol. 1, no. 6, pp. 249-255, Dec 1991.
  48. G.M. Blair, "Personal Time Management for Busy Managers", IEE Engineering Management Journal , vol. 2, no. 1, pp. 33-38, Feb 1992.
  49. G.M. Blair, "How to Build Quality into your Team", IEE Engineering Management Journal , vol. 2, no. 2, pp. 79-84, Apr 1992.
  50. G.M. Blair, "How to Write Right", IEE Engineering Management Journal , vol. 2, no. 3, pp. 111-5, June 1992.
  51. G.M. Blair, "The Art of Delegation", IEE Engineering Management Journal , vol. 2, no. 4, pp. 165-169, Aug 1992.
  52. G.M. Blair, "The Human Factor", IEE Engineering Management Journal , vol. 2, no. 5, pp. 219-223, Oct 1992.
  53. G.M. Blair, "Conversation as Communication", IEE Engineering Management Journal , vol. 2, no. 6, pp. 265-270, Dec 1992.
  54. G.M. Blair, "Planning a Project", IEE Engineering Management Journal , vol. 3, no. 1, pp. 15-21, Feb 1993.
  55. G.M. Blair, "What makes a Great Manager", IEE Engineering Management Journal , vol. 3, no. 2, pp. 65-70, Apr 1993.
  56. G.M. Blair, "Laying the Foundations for Effective Teamwork", IEE Engineering Science and Education Journal , vol. 2, no. 1, pp. 15-19, Feb 1993.
  57. G.M. Blair and C.M. Robinson, "Professional Skills for First-Year Engineering Students", IEE Engineering Science and Education Journal , vol. 4, no. 1, pp. 23-28, Feb 1995.
  58. G.M. Blair, "Becoming a Great Manager", Management Development Review , vol. 6, no. 4, pp. 3-5, 1993.
  59. G.M. Blair, "Delegating Training", Training Officer , vol. 30, no. 1, pp. 6-8, 1994.
  60. G.M. Blair, "Professional-skills training in electrical engineering", CVCP/Universities Staff Development and Training Unit , 1992.

    12th December 1997